Now, armed with this information, we can discuss the relationship between the CPU address bus and the memory address bus. The CPU has 24 address pins if it is a '286, and 32 address pins if it's the '386, '486, or Pentium; 36 address pins if it's a Pentium Pro. The RAM chips obviously have far fewer address pins than the CPU; so to convert the CPU address to RAM RAS & CAS addresses, the CPU address bus enters a memory controller. The memory controller converts the CPU address signals to RAS addresses, CAS addresses, and BANK addresses (more on BANK addressing later). Let's suppose our computer was a '286 design supporting only 4 banks of memory. (Even though the 80286 is obsolete, describing it's memory configuration is perfect for this example.) This memory can consist of any combination of 64k, 256k, 1M, and 4M chips, but each bank must be populated with a consistent size of RAM chips. To support 4M memory chips, our memory controller must provide signals to 11 RAS addresses, plus 11 CAS addresses. This takes 22 of our 24 address lines available from the CPU. The remaining two address lines from the CPU are interpreted by the memory controller to select which BANK of memory to access. Figure 2 shows a hypothetical relationship between the CPU address bus and the memory address bus. According to this diagram, anytime the CPU asserts A00..A10, the RAM chip receives a column address. Likewise, anytime the CPU asserts A13..A23, the RAM chip receives a row address. CPU address lines A11 and A12 are used to select between RAM banks. Since our hypothetical computer supports only four banks of memory, when <A12,A11>=00, the memory controller selects BANK0; when <A12,A11>=01, the memory controller selects BANK1; <A12,A11>=10 the memory controller selects BANK2; and <A12,A11>=11, the memory controller selects BANK3. With this information, we can write to any row of any bank of RAM chips in the computer. In this manner, we can detect how many banks of RAM are installed in the computer, and determine the size of each RAM bank. All that we need to complete our RAM sizing discussion is some theory and algorithms to apply our knowledge.
In our hypothetical computer, the memory controller multiplexes the addresses according to the size of RAM chips. Figure 2 showed the CPU address bus/memory address bus relationship for 4M chips. When the chip size is smaller than 4M, the relationship between the CPU address bus and RAM address bus changes. In our computer, chip size in each RAM bank is programmable; therefore we need to determine the size of the chip in the socket and subsequently re-program the memory controller before we can have full access to all the memory in the computer.
To size memory, we start by assuming each RAM bank has the maximum size RAM chips which are supported by the memory controller. In our hypothetical computer, the memory controller supports up to 4M chips. Therefore, we program the memory controller for four banks of 4 MB chips. By programming the memory controller for this configuration, we can detect when a smaller memory chip is installed in the socket. But before we check the size of the chip, we need to detect if any RAM is in the socket. RAM detection is achieved by writing to the RAM bank, completely reloading the prefetch queue, and checking the value we wrote. If we get back the value we wrote, we have sufficiently determined that RAM is available for that bank of memory. And then we can check the size of the chip.
Figure 1 - 64k, 256k, 1M, 4M,
64M, 256M
DRAM pin out
Figure 2 - CPU Address Bus Conversion
for 4 MB DRAM Chips