Figure 2

+-----------------------------------------------+
|                                               |
|  4          3 3  32 2  222 2 2              0 |
|  7          2 1  09 8  765 4 3              0 |
| +------------+-+---+-+----+-+----------------+|
| |16-bit Limit|P|DPL|S|Type|A|24-bit base addr||
| +------------+-+---+-+----+-+----------------+|
|                                               |
| (a) 80286 Descriptor Cache Register           |
|                                               |
+-----------------------------------------------+
|                                               |
|  3 2 2  22 2  111 1 1 1 1 0 Bit               |
|  1 4 3  21 0  987 6 5 4 3 0 Offset            |
| +---+-+---+-+----+-+-+-+---+                  |
| | 0 |P|DPL|S|Type|A|0|D| 0 |                  |
| +---+-+---+-+----+-+-+-+---+                  |
|                                               |
|  6                        3 Bit               |
|  3                        2 Offset            |
| +--------------------------+                  |
| | 32-bit physical address  |                  |
| +--------------------------+                  |
|                                               |
|  9                        6 Bit               |
|  5                        4 Offset            |
| +--------------------------+                  |
| | 32-bit segment limit     |                  |
| +--------------------------+                  |
|                                               |
| P    \                                        |
| DPL   |                                       |
| S      > See the appropriate Intel reference  |
| Type   >  manuals for a description of these  |
| A     |   fields.                             |
| D    /                                        |
|                                               |
| (b) 80386/80486 Descriptor Cache Register     |
|                                               |
+-----------------------------------------------+